Friday, September 5th, 2014

Test Chips Show Successful Read and Program Capability With Excellent Programmed Cell Characteristics for 1T-Fuse(TM) Cells Implemented in FinFET Architecture

OTTAWA, ON -- (Marketwired) -- Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that it successfully demonstrated read and write capability for its 1T-OTP bit-cell architecture on test silicon fabricated in a 16nm CMOS FinFET process.

"Sidense's embedded one-time programmable memory macros have been licensed in customers' designs from 0.18-micron down to 28nm and have been proven at the 20nm process node as well," said Wlodek Kurjanowicz, Sidense Founder and CTO. "Our split-channel 1T-OTP macros were designed to be highly scalable with shrinking process nodes. It is gratifying to see our theories proven in new transistor architectures such as FinFET."

The 3D 16nm FinFET architecture provides higher performance, lower dynamic power and smaller transistor geometries than standard transistors at 20nm, the latter benefit allowing designers to put more functions on a silicon chip. More importantly FinFETs eliminate short-channel effects and the subsequent high leakage currents that limit device scalability of traditional planar transistors. These attributes make devices designed with FinFETs very attractive for market segments that require high performance and minimum power dissipation, such as mobile computing, communications and high-end processor nodes on IoT networks.

Preliminary test results at 16nm confirm correct bit-cell operation with a programming voltage comparable to Sidense 1T-OTP at 28nm with 10X lower leakage current. Programmed bit-cell characteristics are as good as or better than those for 20nm and 28nm bit cells with very large margins between programmed and un-programmed cells and with excellent post-bake bit-cell stability.

"With its enhanced speed performance and reduced power dissipation, TSMC's 16nm technology is an excellent choice for mobile device chip designs," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "NVM is now, and will continue to be, a key component in mobile devices, and it is encouraging to see good initial test results on Sidense OTP devices at this process node."

About Sidense Corp.
Sidense Corp. provides very dense, highly reliable and secure non-volatile one-time programmable (OTP) Logic Non-Volatile Memory (LNVM) IP for use in standard-logic CMOS processes. The Company, with over 120 patents granted or pending, licenses OTP memory IP based on its innovative one-transistor 1T-Fuse(tm) bit cell, which does not require extra masks or process steps to manufacture. Sidense 1T-OTP macros provide a better field-programmable, reliable and cost-effective solution than flash, mask ROM, eFuse and other embedded and off-chip NVM technologies for many code storage, encryption key, analog trimming and device configuration uses.

125 companies, including many of the top fabless semiconductor manufacturers and IDMs, have adopted Sidense 1T-OTP as their NVM solution in more than 400 designs. Customers are realizing outstanding savings in solution cost and power consumption along with better security and reliability for applications ranging from mobile and consumer devices to high-temperature, high-reliability automotive and industrial electronics. The IP is offered at and supported by all top-tier semiconductor foundries and selected IDMs. Sidense is headquartered in Ottawa, Canada with sales offices worldwide. For more information, please visit

Media Contacts:
Susan Cain
Cain Communications for Sidense
Tel: 408-393-4794
Email: [email protected]

Jim Lipman
Tel: 925-606-1370
Email: [email protected]


Sidense, OTP, LNVM, IP, code storage, encryption key, analog trimming, one-time programmable



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